feature. See also
. The project being documented here (as the example) is the Zig library itself.
x86.detectAMDProcessor
fn detectAMDProcessor(cpu: Target.Cpu, family: u32, model: u32) ?*const Target.Cpu.Model
File
Code
fn detectAMDProcessor(cpu: Target.Cpu, family: u32, model: u32) ?*const Target.Cpu.Model {
return switch (family) {
4 => &Target.x86.cpu.i486,
5 => switch (model) {
6, 7 => &Target.x86.cpu.k6,
8 => &Target.x86.cpu.k6_2,
9, 13 => &Target.x86.cpu.k6_3,
10 => &Target.x86.cpu.geode,
else => &Target.x86.cpu.pentium,
},
6 => if (cpu.has(.x86, .sse))
&Target.x86.cpu.athlon_xp
else
&Target.x86.cpu.athlon,
15 => if (cpu.has(.x86, .sse3))
&Target.x86.cpu.k8_sse3
else
&Target.x86.cpu.k8,
16, 18 => &Target.x86.cpu.amdfam10,
20 => &Target.x86.cpu.btver1,
21 => switch (model) {
0x60...0x7f => &Target.x86.cpu.bdver4,
0x30...0x3f => &Target.x86.cpu.bdver3,
0x02, 0x10...0x1f => &Target.x86.cpu.bdver2,
else => &Target.x86.cpu.bdver1,
},
22 => &Target.x86.cpu.btver2,
23 => switch (model) {
0x30...0x3f, 0x47, 0x60...0x6f, 0x70...0x7f, 0x84...0x87, 0x90...0x9f, 0xa0...0xaf => &Target.x86.cpu.znver2,
else => &Target.x86.cpu.znver1,
},
25 => switch (model) {
0x10...0x1f, 0x60...0x6f, 0x70...0x7f, 0xa0...0xaf => &Target.x86.cpu.znver4,
else => &Target.x86.cpu.znver3,
},
26 => &Target.x86.cpu.znver5,
else => null,
};
}