RiscvCpuinfoImpl

const RiscvCpuinfoImpl = struct

File

Code

const RiscvCpuinfoImpl = struct {
    model: ?*const Target.Cpu.Model = null,

    const cpu_names = .{
        .{ "andestech,ax45mp", &Target.riscv.cpu.andes_ax45 },
        .{ "sifive,p550", &Target.riscv.cpu.sifive_p550 },
        .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
        .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
        .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
        .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
        .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
        .{ "sifive,x280", &Target.riscv.cpu.sifive_x280 },
        .{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },
        .{ "spacemit,x100", &Target.riscv.cpu.spacemit_x100 },
    };

    fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {
        if (mem.eql(u8, key, "uarch")) {
            inline for (cpu_names) |pair| {
                if (mem.eql(u8, value, pair[0])) {
                    self.model = pair[1];
                    break;
                }
            }
            return false;
        }

        return true;
    }

    fn finalize(self: *const RiscvCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu {
        const model = self.model orelse return null;
        return Target.Cpu{
            .arch = arch,
            .model = model,
            .features = model.features,
        };
    }
}