Processor feature enumeration.
pub const PF = enum(DWORD)pub const PF = enum(DWORD) {
/// On a Pentium, a floating-point precision error can occur in rare circumstances.
FLOATING_POINT_PRECISION_ERRATA = 0,
/// Floating-point operations are emulated using software emulator.
/// This function returns a nonzero value if floating-point operations are emulated; otherwise, it returns zero.
FLOATING_POINT_EMULATED = 1,
/// The atomic compare and exchange operation (cmpxchg) is available.
COMPARE_EXCHANGE_DOUBLE = 2,
/// The MMX instruction set is available.
MMX_INSTRUCTIONS_AVAILABLE = 3,
PPC_MOVEMEM_64BIT_OK = 4,
ALPHA_BYTE_INSTRUCTIONS = 5,
/// The SSE instruction set is available.
XMMI_INSTRUCTIONS_AVAILABLE = 6,
/// The 3D-Now instruction is available.
@"3DNOW_INSTRUCTIONS_AVAILABLE" = 7,
/// The RDTSC instruction is available.
RDTSC_INSTRUCTION_AVAILABLE = 8,
/// The processor is PAE-enabled.
PAE_ENABLED = 9,
/// The SSE2 instruction set is available.
XMMI64_INSTRUCTIONS_AVAILABLE = 10,
SSE_DAZ_MODE_AVAILABLE = 11,
/// Data execution prevention is enabled.
NX_ENABLED = 12,
/// The SSE3 instruction set is available.
SSE3_INSTRUCTIONS_AVAILABLE = 13,
/// The atomic compare and exchange 128-bit operation (cmpxchg16b) is available.
COMPARE_EXCHANGE128 = 14,
/// The atomic compare 64 and exchange 128-bit operation (cmp8xchg16) is available.
COMPARE64_EXCHANGE128 = 15,
/// The processor channels are enabled.
CHANNELS_ENABLED = 16,
/// The processor implements the XSAVI and XRSTOR instructions.
XSAVE_ENABLED = 17,
/// The VFP/Neon: 32 x 64bit register bank is present.
/// This flag has the same meaning as PF_ARM_VFP_EXTENDED_REGISTERS.
ARM_VFP_32_REGISTERS_AVAILABLE = 18,
/// This ARM processor implements the ARM v8 NEON instruction set.
ARM_NEON_INSTRUCTIONS_AVAILABLE = 19,
/// Second Level Address Translation is supported by the hardware.
SECOND_LEVEL_ADDRESS_TRANSLATION = 20,
/// Virtualization is enabled in the firmware and made available by the operating system.
VIRT_FIRMWARE_ENABLED = 21,
/// RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE instructions are available.
RDWRFSGBASE_AVAILABLE = 22,
/// _fastfail() is available.
FASTFAIL_AVAILABLE = 23,
/// The divide instruction_available.
ARM_DIVIDE_INSTRUCTION_AVAILABLE = 24,
/// The 64-bit load/store atomic instructions are available.
ARM_64BIT_LOADSTORE_ATOMIC = 25,
/// The external cache is available.
ARM_EXTERNAL_CACHE_AVAILABLE = 26,
/// The floating-point multiply-accumulate instruction is available.
ARM_FMAC_INSTRUCTIONS_AVAILABLE = 27,
RDRAND_INSTRUCTION_AVAILABLE = 28,
/// This ARM processor implements the ARM v8 instructions set.
ARM_V8_INSTRUCTIONS_AVAILABLE = 29,
/// This ARM processor implements the ARM v8 extra cryptographic instructions (i.e., AES, SHA1 and SHA2).
ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE = 30,
/// This ARM processor implements the ARM v8 extra CRC32 instructions.
ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE = 31,
RDTSCP_INSTRUCTION_AVAILABLE = 32,
RDPID_INSTRUCTION_AVAILABLE = 33,
/// This ARM processor implements the ARM v8.1 atomic instructions (e.g., CAS, SWP).
ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE = 34,
MONITORX_INSTRUCTION_AVAILABLE = 35,
/// The SSSE3 instruction set is available.
SSSE3_INSTRUCTIONS_AVAILABLE = 36,
/// The SSE4_1 instruction set is available.
SSE4_1_INSTRUCTIONS_AVAILABLE = 37,
/// The SSE4_2 instruction set is available.
SSE4_2_INSTRUCTIONS_AVAILABLE = 38,
/// The AVX instruction set is available.
AVX_INSTRUCTIONS_AVAILABLE = 39,
/// The AVX2 instruction set is available.
AVX2_INSTRUCTIONS_AVAILABLE = 40,
/// The AVX512F instruction set is available.
AVX512F_INSTRUCTIONS_AVAILABLE = 41,
ERMS_AVAILABLE = 42,
/// This ARM processor implements the ARM v8.2 Dot Product (DP) instructions.
ARM_V82_DP_INSTRUCTIONS_AVAILABLE = 43,
/// This ARM processor implements the ARM v8.3 JavaScript conversion (JSCVT) instructions.
ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE = 44,
/// This Arm processor implements the Arm v8.3 LRCPC instructions (for example, LDAPR). Note that certain Arm v8.2 CPUs may optionally support the LRCPC instructions.
ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE = 45,
/// This Arm processor implements the SVE (Scalable Vector Extension) instructions (FEAT_SVE).
ARM_SVE_INSTRUCTIONS_AVAILABLE = 46,
/// This Arm processor implements the SVE2 instructions (FEAT_SVE2).
ARM_SVE2_INSTRUCTIONS_AVAILABLE = 47,
/// This Arm processor implements the SVE2.1 instructions (FEAT_SVE2p1).
ARM_SVE2_1_INSTRUCTIONS_AVAILABLE = 48,
/// This Arm processor implements the SVE AES instructions (FEAT_SVE_AES).
ARM_SVE_AES_INSTRUCTIONS_AVAILABLE = 49,
/// This Arm processor implements the SVE 128-bit polynomial multiply long instructions (FEAT_SVE_PMULL128).
ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE = 50,
/// This Arm processor implements the SVE bit permute instructions (FEAT_SVE_BitPerm).
ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE = 51,
/// This Arm processor implements the SVE BF16 (BFloat16) instructions (FEAT_BF16).
ARM_SVE_BF16_INSTRUCTIONS_AVAILABLE = 52,
/// This Arm processor implements the SVE EBF16 (Extended BFloat16) instructions (FEAT_EBF16).
ARM_SVE_EBF16_INSTRUCTIONS_AVAILABLE = 53,
/// This Arm processor implements the SVE B16B16 instructions (FEAT_SVE_B16B16).
ARM_SVE_B16B16_INSTRUCTIONS_AVAILABLE = 54,
/// This Arm processor implements the SVE SHA-3 cryptographic instructions (FEAT_SVE_SHA3).
ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE = 55,
/// This Arm processor implements the SVE SM4 cryptographic instructions (FEAT_SVE_SM4).
ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE = 56,
/// This Arm processor implements the SVE I8MM (Int8 matrix multiply) instructions (FEAT_I8MM).
ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE = 57,
/// This Arm processor implements the SVE F32MM (FP32 matrix multiply) instructions (FEAT_F32MM).
ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE = 58,
/// This Arm processor implements the SVE F64MM (FP64 matrix multiply) instructions (FEAT_F64MM).
ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE = 59,
/// This x64 processor implements the BMI2 instruction set.
BMI2_INSTRUCTIONS_AVAILABLE = 60,
/// This x64 processor implements the MOVDIR64B instruction.
MOVDIR64B_INSTRUCTION_AVAILABLE = 61,
/// This Arm processor implements the LSE2 atomic instructions (FEAT_LSE2).
ARM_LSE2_AVAILABLE = 62,
/// This Arm processor implements the SHA-3 cryptographic instructions (FEAT_SHA3).
ARM_SHA3_INSTRUCTIONS_AVAILABLE = 64,
/// This Arm processor implements the SHA-512 cryptographic instructions (FEAT_SHA512).
ARM_SHA512_INSTRUCTIONS_AVAILABLE = 65,
/// This Arm processor implements the I8MM (Int8 matrix multiply) NEON instructions (FEAT_I8MM).
ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE = 66,
/// This Arm processor implements the FP16 (half-precision floating point) NEON instructions (FEAT_FP16).
ARM_V82_FP16_INSTRUCTIONS_AVAILABLE = 67,
/// This Arm processor implements the BF16 (BFloat16) NEON instructions (FEAT_BF16).
ARM_V86_BF16_INSTRUCTIONS_AVAILABLE = 68,
/// This Arm processor implements the EBF16 (Extended BFloat16) NEON instructions (FEAT_EBF16).
ARM_V86_EBF16_INSTRUCTIONS_AVAILABLE = 69,
/// This Arm processor implements the SME (Scalable Matrix Extension) instructions (FEAT_SME).
ARM_SME_INSTRUCTIONS_AVAILABLE = 70,
/// This Arm processor implements the SME2 instructions (FEAT_SME2).
ARM_SME2_INSTRUCTIONS_AVAILABLE = 71,
/// This Arm processor implements the SME2.1 instructions (FEAT_SME2p1).
ARM_SME2_1_INSTRUCTIONS_AVAILABLE = 72,
/// This Arm processor implements the SME2.2 instructions (FEAT_SME2p2).
ARM_SME2_2_INSTRUCTIONS_AVAILABLE = 73,
/// This Arm processor implements the SVE AES instructions when in Streaming SVE mode (FEAT_SSVE_AES).
ARM_SME_AES_INSTRUCTIONS_AVAILABLE = 74,
/// This Arm processor implements the SVE bit permute instructions when in Streaming SVE mode (FEAT_SSVE_BitPerm).
ARM_SME_SBITPERM_INSTRUCTIONS_AVAILABLE = 75,
/// This Arm processor implements the SVE FMMLA (widening, 4-way, FP8 to FP16) instruction when in Streaming SVE mode (FEAT_SSVE_F8F16MM).
ARM_SME_SF8MM4_INSTRUCTIONS_AVAILABLE = 76,
/// This Arm processor implements the SVE FMMLA (widening, 8-way, FP8 to FP32) instruction when in Streaming SVE mode (FEAT_SSVE_F8F32MM).
ARM_SME_SF8MM8_INSTRUCTIONS_AVAILABLE = 77,
/// This Arm processor implements the SVE2 FP8DOT2 instructions when in Streaming SVE mode (FEAT_SSVE_FP8DOT2).
ARM_SME_SF8DP2_INSTRUCTIONS_AVAILABLE = 78,
/// This Arm processor implements the SVE2 FP8DOT4 instructions when in Streaming SVE mode (FEAT_SSVE_FP8DOT4).
ARM_SME_SF8DP4_INSTRUCTIONS_AVAILABLE = 79,
/// This Arm processor implements the SVE2 FP8FMA instructions when in Streaming SVE mode (FEAT_SSVE_FP8FMA).
ARM_SME_SF8FMA_INSTRUCTIONS_AVAILABLE = 80,
/// This Arm processor implements the SME F8F32 instructions (FEAT_SME_F8F32).
ARM_SME_F8F32_INSTRUCTIONS_AVAILABLE = 81,
/// This Arm processor implements the SME F8F16 instructions (FEAT_SME_F8F16).
ARM_SME_F8F16_INSTRUCTIONS_AVAILABLE = 82,
/// This Arm processor implements the SME F16F16 instructions (FEAT_SME_F16F16).
ARM_SME_F16F16_INSTRUCTIONS_AVAILABLE = 83,
/// This Arm processor implements the SME B16B16 instructions (FEAT_SME_B16B16).
ARM_SME_B16B16_INSTRUCTIONS_AVAILABLE = 84,
/// This Arm processor implements the SME F64F64 instructions (FEAT_SME_F64F64).
ARM_SME_F64F64_INSTRUCTIONS_AVAILABLE = 85,
/// This Arm processor implements the SME I16I64 instructions (FEAT_SME_I16I64).
ARM_SME_I16I64_INSTRUCTIONS_AVAILABLE = 86,
/// This Arm processor implements the SME LUTv2 instructions (FEAT_SME_LUTv2).
ARM_SME_LUTv2_INSTRUCTIONS_AVAILABLE = 87,
/// This Arm processor implements SME FA64 (Full AArch64 instruction set when in Streaming SVE mode) (FEAT_SME_FA64).
ARM_SME_FA64_INSTRUCTIONS_AVAILABLE = 88,
/// This x64 processor implements the UMONITOR instruction.
UMONITOR_INSTRUCTION_AVAILABLE = 89,
}