pub const IMAGE = structpub const IMAGE = struct {
pub const DIRECTORY_ENTRY = enum(u32) {
/// Export Directory
EXPORT = 0,
/// Import Directory
IMPORT = 1,
/// Resource Directory
RESOURCE = 2,
/// Exception Directory
EXCEPTION = 3,
/// Security Directory
SECURITY = 4,
/// Base Relocation Table
BASERELOC = 5,
/// Debug Directory
DEBUG = 6,
/// Architecture Specific Data
ARCHITECTURE = 7,
/// RVA of GP
GLOBALPTR = 8,
/// TLS Directory
TLS = 9,
/// Load Configuration Directory
LOAD_CONFIG = 10,
/// Bound Import Directory in headers
BOUND_IMPORT = 11,
/// Import Address Table
IAT = 12,
/// Delay Load Import Descriptors
DELAY_IMPORT = 13,
/// COM Runtime descriptor
COM_DESCRIPTOR = 14,
/// must be zero
RESERVED = 15,
_,
pub const len = @typeInfo(IMAGE.DIRECTORY_ENTRY).@"enum".field_names.len;
};
pub const FILE = struct {
/// Machine Types
/// The Machine field has one of the following values, which specify the CPU type.
/// An image file can be run only on the specified machine or on a system that emulates the specified machine.
pub const MACHINE = enum(u16) {
/// The content of this field is assumed to be applicable to any machine type
UNKNOWN = 0x0,
/// Alpha AXP, 32-bit address space
ALPHA = 0x184,
/// Alpha 64, 64-bit address space
ALPHA64 = 0x284,
/// Matsushita AM33
AM33 = 0x1d3,
/// x64
AMD64 = 0x8664,
/// ARM little endian
ARM = 0x1c0,
/// ARM64 little endian
ARM64 = 0xaa64,
/// ABI that enables interoperability between native ARM64 and emulated x64 code.
ARM64EC = 0xA641,
/// Binary format that allows both native ARM64 and ARM64EC code to coexist in the same file.
ARM64X = 0xA64E,
/// ARM Thumb-2 little endian
ARMNT = 0x1c4,
/// EFI byte code
EBC = 0xebc,
/// Intel 386 or later processors and compatible processors
I386 = 0x14c,
/// Intel Itanium processor family
IA64 = 0x200,
/// LoongArch 32-bit processor family
LOONGARCH32 = 0x6232,
/// LoongArch 64-bit processor family
LOONGARCH64 = 0x6264,
/// Mitsubishi M32R little endian
M32R = 0x9041,
/// MIPS16
MIPS16 = 0x266,
/// MIPS with FPU
MIPSFPU = 0x366,
/// MIPS16 with FPU
MIPSFPU16 = 0x466,
/// Power PC little endian
POWERPC = 0x1f0,
/// Power PC with floating point support
POWERPCFP = 0x1f1,
/// MIPS I compatible 32-bit big endian
R3000BE = 0x160,
/// MIPS I compatible 32-bit little endian
R3000 = 0x162,
/// MIPS III compatible 64-bit little endian
R4000 = 0x166,
/// MIPS IV compatible 64-bit little endian
R10000 = 0x168,
/// RISC-V 32-bit address space
RISCV32 = 0x5032,
/// RISC-V 64-bit address space
RISCV64 = 0x5064,
/// RISC-V 128-bit address space
RISCV128 = 0x5128,
/// Hitachi SH3
SH3 = 0x1a2,
/// Hitachi SH3 DSP
SH3DSP = 0x1a3,
/// Hitachi SH4
SH4 = 0x1a6,
/// Hitachi SH5
SH5 = 0x1a8,
/// Thumb
THUMB = 0x1c2,
/// MIPS little-endian WCE v2
WCEMIPSV2 = 0x169,
_,
/// AXP 64 (Same as Alpha 64)
pub const AXP64: IMAGE.FILE.MACHINE = .ALPHA64;
pub fn RelocationType(comptime machine: IMAGE.FILE.MACHINE) type {
return switch (machine) {
.AMD64,
=> REL.AMD64,
.ARM,
.ARMNT,
=> REL.ARM,
.ARM64,
.ARM64EC,
.ARM64X,
=> REL.ARM64,
.I386 => REL.I386,
.IA64 => REL.IA64,
.M32R => REL.M32R,
.MIPS16,
.MIPSFPU,
.MIPSFPU16,
=> REL.MIPS,
.POWERPC,
.POWERPCFP,
=> REL.PPC,
.SH3,
.SH3DSP,
.SH4,
.SH5,
=> REL.SH,
else => void,
};
}
};
};
pub const REL = struct {
/// x64 Processors
/// The following relocation type indicators are defined for x64 and compatible processors.
pub const AMD64 = enum(u16) {
/// The relocation is ignored.
ABSOLUTE = 0x0000,
/// The 64-bit VA of the relocation target.
ADDR64 = 0x0001,
/// The 32-bit VA of the relocation target.
ADDR32 = 0x0002,
/// The 32-bit address without an image base (RVA).
ADDR32NB = 0x0003,
/// The 32-bit relative address from the byte following the relocation.
REL32 = 0x0004,
/// The 32-bit address relative to byte distance 1 from the relocation.
REL32_1 = 0x0005,
/// The 32-bit address relative to byte distance 2 from the relocation.
REL32_2 = 0x0006,
/// The 32-bit address relative to byte distance 3 from the relocation.
REL32_3 = 0x0007,
/// The 32-bit address relative to byte distance 4 from the relocation.
REL32_4 = 0x0008,
/// The 32-bit address relative to byte distance 5 from the relocation.
REL32_5 = 0x0009,
/// The 16-bit section index of the section that contains the target.
/// This is used to support debugging information.
SECTION = 0x000A,
/// The 32-bit offset of the target from the beginning of its section.
/// This is used to support debugging information and static thread local storage.
SECREL = 0x000B,
/// A 7-bit unsigned offset from the base of the section that contains the target.
SECREL7 = 0x000C,
/// CLR tokens.
TOKEN = 0x000D,
/// A 32-bit signed span-dependent value emitted into the object.
SREL32 = 0x000E,
/// A pair that must immediately follow every span-dependent value.
PAIR = 0x000F,
/// A 32-bit signed span-dependent value that is applied at link time.
SSPAN32 = 0x0010,
_,
};
/// ARM Processors
/// The following relocation type indicators are defined for ARM processors.
pub const ARM = enum(u16) {
/// The relocation is ignored.
ABSOLUTE = 0x0000,
/// The 32-bit VA of the target.
ADDR32 = 0x0001,
/// The 32-bit RVA of the target.
ADDR32NB = 0x0002,
/// The 24-bit relative displacement to the target.
BRANCH24 = 0x0003,
/// The reference to a subroutine call.
/// The reference consists of two 16-bit instructions with 11-bit offsets.
BRANCH11 = 0x0004,
/// The 32-bit relative address from the byte following the relocation.
REL32 = 0x000A,
/// The 16-bit section index of the section that contains the target.
/// This is used to support debugging information.
SECTION = 0x000E,
/// The 32-bit offset of the target from the beginning of its section.
/// This is used to support debugging information and static thread local storage.
SECREL = 0x000F,
/// The 32-bit VA of the target.
/// This relocation is applied using a MOVW instruction for the low 16 bits followed by a MOVT for the high 16 bits.
MOV32 = 0x0010,
/// The 32-bit VA of the target.
/// This relocation is applied using a MOVW instruction for the low 16 bits followed by a MOVT for the high 16 bits.
THUMB_MOV32 = 0x0011,
/// The instruction is fixed up with the 21-bit relative displacement to the 2-byte aligned target.
/// The least significant bit of the displacement is always zero and is not stored.
/// This relocation corresponds to a Thumb-2 32-bit conditional B instruction.
THUMB_BRANCH20 = 0x0012,
Unused = 0x0013,
/// The instruction is fixed up with the 25-bit relative displacement to the 2-byte aligned target.
/// The least significant bit of the displacement is zero and is not stored.This relocation corresponds to a Thumb-2 B instruction.
THUMB_BRANCH24 = 0x0014,
/// The instruction is fixed up with the 25-bit relative displacement to the 4-byte aligned target.
/// The low 2 bits of the displacement are zero and are not stored.
/// This relocation corresponds to a Thumb-2 BLX instruction.
THUMB_BLX23 = 0x0015,
/// The relocation is valid only when it immediately follows a ARM_REFHI or THUMB_REFHI.
/// Its SymbolTableIndex contains a displacement and not an index into the symbol table.
PAIR = 0x0016,
_,
};
/// ARM64 Processors
/// The following relocation type indicators are defined for ARM64 processors.
pub const ARM64 = enum(u16) {
/// The relocation is ignored.
ABSOLUTE = 0x0000,
/// The 32-bit VA of the target.
ADDR32 = 0x0001,
/// The 32-bit RVA of the target.
ADDR32NB = 0x0002,
/// The 26-bit relative displacement to the target, for B and BL instructions.
BRANCH26 = 0x0003,
/// The page base of the target, for ADRP instruction.
PAGEBASE_REL21 = 0x0004,
/// The 12-bit relative displacement to the target, for instruction ADR
REL21 = 0x0005,
/// The 12-bit page offset of the target, for instructions ADD/ADDS (immediate) with zero shift.
PAGEOFFSET_12A = 0x0006,
/// The 12-bit page offset of the target, for instruction LDR (indexed, unsigned immediate).
PAGEOFFSET_12L = 0x0007,
/// The 32-bit offset of the target from the beginning of its section.
/// This is used to support debugging information and static thread local storage.
SECREL = 0x0008,
/// Bit 0:11 of section offset of the target, for instructions ADD/ADDS (immediate) with zero shift.
SECREL_LOW12A = 0x0009,
/// Bit 12:23 of section offset of the target, for instructions ADD/ADDS (immediate) with zero shift.
SECREL_HIGH12A = 0x000A,
/// Bit 0:11 of section offset of the target, for instruction LDR (indexed, unsigned immediate).
SECREL_LOW12L = 0x000B,
/// CLR token.
TOKEN = 0x000C,
/// The 16-bit section index of the section that contains the target.
/// This is used to support debugging information.
SECTION = 0x000D,
/// The 64-bit VA of the relocation target.
ADDR64 = 0x000E,
/// The 19-bit offset to the relocation target, for conditional B instruction.
BRANCH19 = 0x000F,
/// The 14-bit offset to the relocation target, for instructions TBZ and TBNZ.
BRANCH14 = 0x0010,
/// The 32-bit relative address from the byte following the relocation.
REL32 = 0x0011,
_,
};
/// Hitachi SuperH Processors
/// The following relocation type indicators are defined for SH3 and SH4 processors.
/// SH5-specific relocations are noted as SHM (SH Media).
pub const SH = enum(u16) {
/// The relocation is ignored.
@"3_ABSOLUTE" = 0x0000,
/// A reference to the 16-bit location that contains the VA of the target symbol.
@"3_DIRECT16" = 0x0001,
/// The 32-bit VA of the target symbol.
@"3_DIRECT32" = 0x0002,
/// A reference to the 8-bit location that contains the VA of the target symbol.
@"3_DIRECT8" = 0x0003,
/// A reference to the 8-bit instruction that contains the effective 16-bit VA of the target symbol.
@"3_DIRECT8_WORD" = 0x0004,
/// A reference to the 8-bit instruction that contains the effective 32-bit VA of the target symbol.
@"3_DIRECT8_LONG" = 0x0005,
/// A reference to the 8-bit location whose low 4 bits contain the VA of the target symbol.
@"3_DIRECT4" = 0x0006,
/// A reference to the 8-bit instruction whose low 4 bits contain the effective 16-bit VA of the target symbol.
@"3_DIRECT4_WORD" = 0x0007,
/// A reference to the 8-bit instruction whose low 4 bits contain the effective 32-bit VA of the target symbol.
@"3_DIRECT4_LONG" = 0x0008,
/// A reference to the 8-bit instruction that contains the effective 16-bit relative offset of the target symbol.
@"3_PCREL8_WORD" = 0x0009,
/// A reference to the 8-bit instruction that contains the effective 32-bit relative offset of the target symbol.
@"3_PCREL8_LONG" = 0x000A,
/// A reference to the 16-bit instruction whose low 12 bits contain the effective 16-bit relative offset of the target symbol.
@"3_PCREL12_WORD" = 0x000B,
/// A reference to a 32-bit location that is the VA of the section that contains the target symbol.
@"3_STARTOF_SECTION" = 0x000C,
/// A reference to the 32-bit location that is the size of the section that contains the target symbol.
@"3_SIZEOF_SECTION" = 0x000D,
/// The 16-bit section index of the section that contains the target.
/// This is used to support debugging information.
@"3_SECTION" = 0x000E,
/// The 32-bit offset of the target from the beginning of its section.
/// This is used to support debugging information and static thread local storage.
@"3_SECREL" = 0x000F,
/// The 32-bit RVA of the target symbol.
@"3_DIRECT32_NB" = 0x0010,
/// GP relative.
@"3_GPREL4_LONG" = 0x0011,
/// CLR token.
@"3_TOKEN" = 0x0012,
/// The offset from the current instruction in longwords.
/// If the NOMODE bit is not set, insert the inverse of the low bit at bit 32 to select PTA or PTB.
M_PCRELPT = 0x0013,
/// The low 16 bits of the 32-bit address.
M_REFLO = 0x0014,
/// The high 16 bits of the 32-bit address.
M_REFHALF = 0x0015,
/// The low 16 bits of the relative address.
M_RELLO = 0x0016,
/// The high 16 bits of the relative address.
M_RELHALF = 0x0017,
/// The relocation is valid only when it immediately follows a REFHALF, RELHALF, or RELLO relocation.
/// The SymbolTableIndex field of the relocation contains a displacement and not an index into the symbol table.
M_PAIR = 0x0018,
/// The relocation ignores section mode.
M_NOMODE = 0x8000,
_,
};
/// IBM PowerPC Processors
/// The following relocation type indicators are defined for PowerPC processors.
pub const PPC = enum(u16) {
/// The relocation is ignored.
ABSOLUTE = 0x0000,
/// The 64-bit VA of the target.
ADDR64 = 0x0001,
/// The 32-bit VA of the target.
ADDR32 = 0x0002,
/// The low 24 bits of the VA of the target.
/// This is valid only when the target symbol is absolute and can be sign-extended to its original value.
ADDR24 = 0x0003,
/// The low 16 bits of the target's VA.
ADDR16 = 0x0004,
/// The low 14 bits of the target's VA.
/// This is valid only when the target symbol is absolute and can be sign-extended to its original value.
ADDR14 = 0x0005,
/// A 24-bit PC-relative offset to the symbol's location.
REL24 = 0x0006,
/// A 14-bit PC-relative offset to the symbol's location.
REL14 = 0x0007,
/// The 32-bit RVA of the target.
ADDR32NB = 0x000A,
/// The 32-bit offset of the target from the beginning of its section.
/// This is used to support debugging information and static thread local storage.
SECREL = 0x000B,
/// The 16-bit section index of the section that contains the target.
/// This is used to support debugging information.
SECTION = 0x000C,
/// The 16-bit offset of the target from the beginning of its section.
/// This is used to support debugging information and static thread local storage.
SECREL16 = 0x000F,
/// The high 16 bits of the target's 32-bit VA.
/// This is used for the first instruction in a two-instruction sequence that loads a full address.
/// This relocation must be immediately followed by a PAIR relocation whose SymbolTableIndex contains a signed 16-bit displacement that is added to the upper 16 bits that was taken from the location that is being relocated.
REFHI = 0x0010,
/// The low 16 bits of the target's VA.
REFLO = 0x0011,
/// A relocation that is valid only when it immediately follows a REFHI or SECRELHI relocation.
/// Its SymbolTableIndex contains a displacement and not an index into the symbol table.
PAIR = 0x0012,
/// The low 16 bits of the 32-bit offset of the target from the beginning of its section.
SECRELLO = 0x0013,
/// The 16-bit signed displacement of the target relative to the GP register.
GPREL = 0x0015,
/// The CLR token.
TOKEN = 0x0016,
_,
};
/// Intel 386 Processors
/// The following relocation type indicators are defined for Intel 386 and compatible processors.
pub const I386 = enum(u16) {
/// The relocation is ignored.
ABSOLUTE = 0x0000,
/// Not supported.
DIR16 = 0x0001,
/// Not supported.
REL16 = 0x0002,
/// The target's 32-bit VA.
DIR32 = 0x0006,
/// The target's 32-bit RVA.
DIR32NB = 0x0007,
/// Not supported.
SEG12 = 0x0009,
/// The 16-bit section index of the section that contains the target.
/// This is used to support debugging information.
SECTION = 0x000A,
/// The 32-bit offset of the target from the beginning of its section.
/// This is used to support debugging information and static thread local storage.
SECREL = 0x000B,
/// The CLR token.
TOKEN = 0x000C,
/// A 7-bit offset from the base of the section that contains the target.
SECREL7 = 0x000D,
/// The 32-bit relative displacement to the target.
/// This supports the x86 relative branch and call instructions.
REL32 = 0x0014,
_,
};
/// Intel Itanium Processor Family (IPF)
/// The following relocation type indicators are defined for the Intel Itanium processor family and compatible processors.
/// Note that relocations on instructions use the bundle's offset and slot number for the relocation offset.
pub const IA64 = enum(u16) {
/// The relocation is ignored.
ABSOLUTE = 0x0000,
/// The instruction relocation can be followed by an ADDEND relocation whose value is added to the target address before it is inserted into the specified slot in the IMM14 bundle.
/// The relocation target must be absolute or the image must be fixed.
IMM14 = 0x0001,
/// The instruction relocation can be followed by an ADDEND relocation whose value is added to the target address before it is inserted into the specified slot in the IMM22 bundle.
/// The relocation target must be absolute or the image must be fixed.
IMM22 = 0x0002,
/// The slot number of this relocation must be one (1).
/// The relocation can be followed by an ADDEND relocation whose value is added to the target address before it is stored in all three slots of the IMM64 bundle.
IMM64 = 0x0003,
/// The target's 32-bit VA.
/// This is supported only for /LARGEADDRESSAWARE:NO images.
DIR32 = 0x0004,
/// The target's 64-bit VA.
DIR64 = 0x0005,
/// The instruction is fixed up with the 25-bit relative displacement to the 16-bit aligned target.
/// The low 4 bits of the displacement are zero and are not stored.
PCREL21B = 0x0006,
/// The instruction is fixed up with the 25-bit relative displacement to the 16-bit aligned target.
/// The low 4 bits of the displacement, which are zero, are not stored.
PCREL21M = 0x0007,
/// The LSBs of this relocation's offset must contain the slot number whereas the rest is the bundle address.
/// The bundle is fixed up with the 25-bit relative displacement to the 16-bit aligned target.
/// The low 4 bits of the displacement are zero and are not stored.
PCREL21F = 0x0008,
/// The instruction relocation can be followed by an ADDEND relocation whose value is added to the target address and then a 22-bit GP-relative offset that is calculated and applied to the GPREL22 bundle.
GPREL22 = 0x0009,
/// The instruction is fixed up with the 22-bit GP-relative offset to the target symbol's literal table entry.
/// The linker creates this literal table entry based on this relocation and the ADDEND relocation that might follow.
LTOFF22 = 0x000A,
/// The 16-bit section index of the section contains the target.
/// This is used to support debugging information.
SECTION = 0x000B,
/// The instruction is fixed up with the 22-bit offset of the target from the beginning of its section.
/// This relocation can be followed immediately by an ADDEND relocation, whose Value field contains the 32-bit unsigned offset of the target from the beginning of the section.
SECREL22 = 0x000C,
/// The slot number for this relocation must be one (1).
/// The instruction is fixed up with the 64-bit offset of the target from the beginning of its section.
/// This relocation can be followed immediately by an ADDEND relocation whose Value field contains the 32-bit unsigned offset of the target from the beginning of the section.
SECREL64I = 0x000D,
/// The address of data to be fixed up with the 32-bit offset of the target from the beginning of its section.
SECREL32 = 0x000E,
/// The target's 32-bit RVA.
DIR32NB = 0x0010,
/// This is applied to a signed 14-bit immediate that contains the difference between two relocatable targets.
/// This is a declarative field for the linker that indicates that the compiler has already emitted this value.
SREL14 = 0x0011,
/// This is applied to a signed 22-bit immediate that contains the difference between two relocatable targets.
/// This is a declarative field for the linker that indicates that the compiler has already emitted this value.
SREL22 = 0x0012,
/// This is applied to a signed 32-bit immediate that contains the difference between two relocatable values.
/// This is a declarative field for the linker that indicates that the compiler has already emitted this value.
SREL32 = 0x0013,
/// This is applied to an unsigned 32-bit immediate that contains the difference between two relocatable values.
/// This is a declarative field for the linker that indicates that the compiler has already emitted this value.
UREL32 = 0x0014,
/// A 60-bit PC-relative fixup that always stays as a BRL instruction of an MLX bundle.
PCREL60X = 0x0015,
/// A 60-bit PC-relative fixup.
/// If the target displacement fits in a signed 25-bit field, convert the entire bundle to an MBB bundle with NOP.B in slot 1 and a 25-bit BR instruction (with the 4 lowest bits all zero and dropped) in slot 2.
PCREL60B = 0x0016,
/// A 60-bit PC-relative fixup.
/// If the target displacement fits in a signed 25-bit field, convert the entire bundle to an MFB bundle with NOP.F in slot 1 and a 25-bit (4 lowest bits all zero and dropped) BR instruction in slot 2.
PCREL60F = 0x0017,
/// A 60-bit PC-relative fixup.
/// If the target displacement fits in a signed 25-bit field, convert the entire bundle to an MIB bundle with NOP.I in slot 1 and a 25-bit (4 lowest bits all zero and dropped) BR instruction in slot 2.
PCREL60I = 0x0018,
/// A 60-bit PC-relative fixup.
/// If the target displacement fits in a signed 25-bit field, convert the entire bundle to an MMB bundle with NOP.M in slot 1 and a 25-bit (4 lowest bits all zero and dropped) BR instruction in slot 2.
PCREL60M = 0x0019,
/// A 64-bit GP-relative fixup.
IMMGPREL64 = 0x001a,
/// A CLR token.
TOKEN = 0x001b,
/// A 32-bit GP-relative fixup.
GPREL32 = 0x001c,
/// The relocation is valid only when it immediately follows one of the following relocations: IMM14, IMM22, IMM64, GPREL22, LTOFF22, LTOFF64, SECREL22, SECREL64I, or SECREL32.
/// Its value contains the addend to apply to instructions within a bundle, not for data.
ADDEND = 0x001F,
_,
};
/// MIPS Processors
/// The following relocation type indicators are defined for MIPS processors.
pub const MIPS = enum(u16) {
/// The relocation is ignored.
ABSOLUTE = 0x0000,
/// The high 16 bits of the target's 32-bit VA.
REFHALF = 0x0001,
/// The target's 32-bit VA.
REFWORD = 0x0002,
/// The low 26 bits of the target's VA.
/// This supports the MIPS J and JAL instructions.
JMPADDR = 0x0003,
/// The high 16 bits of the target's 32-bit VA.
/// This is used for the first instruction in a two-instruction sequence that loads a full address.
/// This relocation must be immediately followed by a PAIR relocation whose SymbolTableIndex contains a signed 16-bit displacement that is added to the upper 16 bits that are taken from the location that is being relocated.
REFHI = 0x0004,
/// The low 16 bits of the target's VA.
REFLO = 0x0005,
/// A 16-bit signed displacement of the target relative to the GP register.
GPREL = 0x0006,
/// The same as IMAGE_REL_MIPS_GPREL.
LITERAL = 0x0007,
/// The 16-bit section index of the section contains the target.
/// This is used to support debugging information.
SECTION = 0x000A,
/// The 32-bit offset of the target from the beginning of its section.
/// This is used to support debugging information and static thread local storage.
SECREL = 0x000B,
/// The low 16 bits of the 32-bit offset of the target from the beginning of its section.
SECRELLO = 0x000C,
/// The high 16 bits of the 32-bit offset of the target from the beginning of its section.
/// An IMAGE_REL_MIPS_PAIR relocation must immediately follow this one.
/// The SymbolTableIndex of the PAIR relocation contains a signed 16-bit displacement that is added to the upper 16 bits that are taken from the location that is being relocated.
SECRELHI = 0x000D,
/// The low 26 bits of the target's VA.
/// This supports the MIPS16 JAL instruction.
JMPADDR16 = 0x0010,
/// The target's 32-bit RVA.
REFWORDNB = 0x0022,
/// The relocation is valid only when it immediately follows a REFHI or SECRELHI relocation.
/// Its SymbolTableIndex contains a displacement and not an index into the symbol table.
PAIR = 0x0025,
_,
};
/// Mitsubishi M32R
/// The following relocation type indicators are defined for the Mitsubishi M32R processors.
pub const M32R = enum(u16) {
/// The relocation is ignored.
ABSOLUTE = 0x0000,
/// The target's 32-bit VA.
ADDR32 = 0x0001,
/// The target's 32-bit RVA.
ADDR32NB = 0x0002,
/// The target's 24-bit VA.
ADDR24 = 0x0003,
/// The target's 16-bit offset from the GP register.
GPREL16 = 0x0004,
/// The target's 24-bit offset from the program counter (PC), shifted left by 2 bits and sign-extended
PCREL24 = 0x0005,
/// The target's 16-bit offset from the PC, shifted left by 2 bits and sign-extended
PCREL16 = 0x0006,
/// The target's 8-bit offset from the PC, shifted left by 2 bits and sign-extended
PCREL8 = 0x0007,
/// The 16 MSBs of the target VA.
REFHALF = 0x0008,
/// The 16 MSBs of the target VA, adjusted for LSB sign extension.
/// This is used for the first instruction in a two-instruction sequence that loads a full 32-bit address.
/// This relocation must be immediately followed by a PAIR relocation whose SymbolTableIndex contains a signed 16-bit displacement that is added to the upper 16 bits that are taken from the location that is being relocated.
REFHI = 0x0009,
/// The 16 LSBs of the target VA.
REFLO = 0x000A,
/// The relocation must follow the REFHI relocation.
/// Its SymbolTableIndex contains a displacement and not an index into the symbol table.
PAIR = 0x000B,
/// The 16-bit section index of the section that contains the target.
/// This is used to support debugging information.
SECTION = 0x000C,
/// The 32-bit offset of the target from the beginning of its section.
/// This is used to support debugging information and static thread local storage.
SECREL = 0x000D,
/// The CLR token.
TOKEN = 0x000E,
_,
};
};
}