Produces a Zig AST node by translating a Type, respecting the width, but modifying the signed-ness. Asserts the type is an integer.
fn transTypeIntWidthOf(t: *Translator, qt: QualType, is_signed: bool) TypeError!ZigNode
fn transTypeIntWidthOf(t: *Translator, qt: QualType, is_signed: bool) TypeError!ZigNode {
return ZigTag.type.create(t.arena, loop: switch (qt.base(t.comp).type) {
.int => |int_ty| switch (int_ty) {
.char, .schar, .uchar => if (is_signed) "i8" else "u8",
.short, .ushort => if (is_signed) "c_short" else "c_ushort",
.int, .uint => if (is_signed) "c_int" else "c_uint",
.long, .ulong => if (is_signed) "c_long" else "c_ulong",
.long_long, .ulong_long => if (is_signed) "c_longlong" else "c_ulonglong",
.int128, .uint128 => if (is_signed) "i128" else "u128",
},
.bit_int => |bit_int_ty| try std.fmt.allocPrint(t.arena, "{s}{d}", .{
if (is_signed) "i" else "u",
bit_int_ty.bits,
}),
.@"enum" => |enum_ty| blk: {
const tag_ty = enum_ty.tag orelse
break :blk if (is_signed) "c_int" else "c_uint";
continue :loop tag_ty.base(t.comp).type;
},
else => unreachable, // only call this function when it has already been determined the type is int
});
}