pub const IA64 = enum(u16) {
/// The relocation is ignored.
ABSOLUTE = 0x0000,
/// The instruction relocation can be followed by an ADDEND relocation whose value is added to the target address before it is inserted into the specified slot in the IMM14 bundle.
/// The relocation target must be absolute or the image must be fixed.
IMM14 = 0x0001,
/// The instruction relocation can be followed by an ADDEND relocation whose value is added to the target address before it is inserted into the specified slot in the IMM22 bundle.
/// The relocation target must be absolute or the image must be fixed.
IMM22 = 0x0002,
/// The slot number of this relocation must be one (1).
/// The relocation can be followed by an ADDEND relocation whose value is added to the target address before it is stored in all three slots of the IMM64 bundle.
IMM64 = 0x0003,
/// The target's 32-bit VA.
/// This is supported only for /LARGEADDRESSAWARE:NO images.
DIR32 = 0x0004,
/// The target's 64-bit VA.
DIR64 = 0x0005,
/// The instruction is fixed up with the 25-bit relative displacement to the 16-bit aligned target.
/// The low 4 bits of the displacement are zero and are not stored.
PCREL21B = 0x0006,
/// The instruction is fixed up with the 25-bit relative displacement to the 16-bit aligned target.
/// The low 4 bits of the displacement, which are zero, are not stored.
PCREL21M = 0x0007,
/// The LSBs of this relocation's offset must contain the slot number whereas the rest is the bundle address.
/// The bundle is fixed up with the 25-bit relative displacement to the 16-bit aligned target.
/// The low 4 bits of the displacement are zero and are not stored.
PCREL21F = 0x0008,
/// The instruction relocation can be followed by an ADDEND relocation whose value is added to the target address and then a 22-bit GP-relative offset that is calculated and applied to the GPREL22 bundle.
GPREL22 = 0x0009,
/// The instruction is fixed up with the 22-bit GP-relative offset to the target symbol's literal table entry.
/// The linker creates this literal table entry based on this relocation and the ADDEND relocation that might follow.
LTOFF22 = 0x000A,
/// The 16-bit section index of the section contains the target.
/// This is used to support debugging information.
SECTION = 0x000B,
/// The instruction is fixed up with the 22-bit offset of the target from the beginning of its section.
/// This relocation can be followed immediately by an ADDEND relocation, whose Value field contains the 32-bit unsigned offset of the target from the beginning of the section.
SECREL22 = 0x000C,
/// The slot number for this relocation must be one (1).
/// The instruction is fixed up with the 64-bit offset of the target from the beginning of its section.
/// This relocation can be followed immediately by an ADDEND relocation whose Value field contains the 32-bit unsigned offset of the target from the beginning of the section.
SECREL64I = 0x000D,
/// The address of data to be fixed up with the 32-bit offset of the target from the beginning of its section.
SECREL32 = 0x000E,
/// The target's 32-bit RVA.
DIR32NB = 0x0010,
/// This is applied to a signed 14-bit immediate that contains the difference between two relocatable targets.
/// This is a declarative field for the linker that indicates that the compiler has already emitted this value.
SREL14 = 0x0011,
/// This is applied to a signed 22-bit immediate that contains the difference between two relocatable targets.
/// This is a declarative field for the linker that indicates that the compiler has already emitted this value.
SREL22 = 0x0012,
/// This is applied to a signed 32-bit immediate that contains the difference between two relocatable values.
/// This is a declarative field for the linker that indicates that the compiler has already emitted this value.
SREL32 = 0x0013,
/// This is applied to an unsigned 32-bit immediate that contains the difference between two relocatable values.
/// This is a declarative field for the linker that indicates that the compiler has already emitted this value.
UREL32 = 0x0014,
/// A 60-bit PC-relative fixup that always stays as a BRL instruction of an MLX bundle.
PCREL60X = 0x0015,
/// A 60-bit PC-relative fixup.
/// If the target displacement fits in a signed 25-bit field, convert the entire bundle to an MBB bundle with NOP.B in slot 1 and a 25-bit BR instruction (with the 4 lowest bits all zero and dropped) in slot 2.
PCREL60B = 0x0016,
/// A 60-bit PC-relative fixup.
/// If the target displacement fits in a signed 25-bit field, convert the entire bundle to an MFB bundle with NOP.F in slot 1 and a 25-bit (4 lowest bits all zero and dropped) BR instruction in slot 2.
PCREL60F = 0x0017,
/// A 60-bit PC-relative fixup.
/// If the target displacement fits in a signed 25-bit field, convert the entire bundle to an MIB bundle with NOP.I in slot 1 and a 25-bit (4 lowest bits all zero and dropped) BR instruction in slot 2.
PCREL60I = 0x0018,
/// A 60-bit PC-relative fixup.
/// If the target displacement fits in a signed 25-bit field, convert the entire bundle to an MMB bundle with NOP.M in slot 1 and a 25-bit (4 lowest bits all zero and dropped) BR instruction in slot 2.
PCREL60M = 0x0019,
/// A 64-bit GP-relative fixup.
IMMGPREL64 = 0x001a,
/// A CLR token.
TOKEN = 0x001b,
/// A 32-bit GP-relative fixup.
GPREL32 = 0x001c,
/// The relocation is valid only when it immediately follows one of the following relocations: IMM14, IMM22, IMM64, GPREL22, LTOFF22, LTOFF64, SECREL22, SECREL64I, or SECREL32.
/// Its value contains the addend to apply to instructions within a bundle, not for data.
ADDEND = 0x001F,
_,
}
Intel Itanium Processor Family (IPF) The following relocation type indicators are defined for the Intel Itanium processor family and compatible processors. Note that relocations on instructions use the bundle's offset and slot number for the relocation offset.