pub const ARM64 = enum(u16) {
/// The relocation is ignored.
ABSOLUTE = 0x0000,
/// The 32-bit VA of the target.
ADDR32 = 0x0001,
/// The 32-bit RVA of the target.
ADDR32NB = 0x0002,
/// The 26-bit relative displacement to the target, for B and BL instructions.
BRANCH26 = 0x0003,
/// The page base of the target, for ADRP instruction.
PAGEBASE_REL21 = 0x0004,
/// The 12-bit relative displacement to the target, for instruction ADR
REL21 = 0x0005,
/// The 12-bit page offset of the target, for instructions ADD/ADDS (immediate) with zero shift.
PAGEOFFSET_12A = 0x0006,
/// The 12-bit page offset of the target, for instruction LDR (indexed, unsigned immediate).
PAGEOFFSET_12L = 0x0007,
/// The 32-bit offset of the target from the beginning of its section.
/// This is used to support debugging information and static thread local storage.
SECREL = 0x0008,
/// Bit 0:11 of section offset of the target, for instructions ADD/ADDS (immediate) with zero shift.
SECREL_LOW12A = 0x0009,
/// Bit 12:23 of section offset of the target, for instructions ADD/ADDS (immediate) with zero shift.
SECREL_HIGH12A = 0x000A,
/// Bit 0:11 of section offset of the target, for instruction LDR (indexed, unsigned immediate).
SECREL_LOW12L = 0x000B,
/// CLR token.
TOKEN = 0x000C,
/// The 16-bit section index of the section that contains the target.
/// This is used to support debugging information.
SECTION = 0x000D,
/// The 64-bit VA of the relocation target.
ADDR64 = 0x000E,
/// The 19-bit offset to the relocation target, for conditional B instruction.
BRANCH19 = 0x000F,
/// The 14-bit offset to the relocation target, for instructions TBZ and TBNZ.
BRANCH14 = 0x0010,
/// The 32-bit relative address from the byte following the relocation.
REL32 = 0x0011,
_,
}
ARM64 Processors The following relocation type indicators are defined for ARM64 processors.