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This is an example of documentation generated by ZigDoc, an alternative to Zig's built-in Auto Doc feature. See also examples in other modes/formats. The project being documented here (as the example) is the Zig standard library. Public Constant

gfx1251

Public Constant
std.Target.amdgcn.cpu.gfx1251
pub const gfx1251: CpuModel = .

File

Target/amdgcn.zig:2756
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    pub const gfx1251: CpuModel = .{
        .name = "gfx1251",
        .llvm_name = "gfx1251",
        .features = featureSet(&[_]Feature{
            .@"1024_addressable_vgprs",
            .@"45_bit_num_records_buffer_resource",
            .@"64_bit_literals",
            .add_min_max_insts,
            .add_sub_u64_insts,
            .addressablelocalmemorysize327680,
            .architected_flat_scratch,
            .architected_sgprs,
            .ashr_pk_insts,
            .atomic_buffer_global_pk_add_f16_insts,
            .atomic_buffer_pk_add_bf16_inst,
            .atomic_ds_pk_add_16_insts,
            .atomic_fadd_no_rtn_insts,
            .atomic_fadd_rtn_insts,
            .atomic_flat_pk_add_16_insts,
            .atomic_fmin_fmax_flat_f64,
            .atomic_fmin_fmax_global_f64,
            .atomic_global_pk_add_bf16_inst,
            .bf16_cvt_insts,
            .bf16_pk_insts,
            .bf16_trans_insts,
            .bitop3_insts,
            .clusters,
            .cube_insts,
            .cumode,
            .cvt_norm_insts,
            .cvt_pk_f16_f32_inst,
            .cvt_pknorm_vop2_insts,
            .cvt_pknorm_vop3_insts,
            .d16_write_vgpr32,
            .dl_insts,
            .dot7_insts,
            .dot8_insts,
            .dpp_64bit,
            .dpp_src1_sgpr,
            .emulated_system_scope_atomics,
            .flat_atomic_fadd_f32_inst,
            .flat_buffer_global_fadd_f64_inst,
            .flat_gvs_mode,
            .fma_mix_bf16_insts,
            .fmacf64_inst,
            .fp8_conversion_insts,
            .fp8e5m3_insts,
            .gfx12,
            .gfx1250_insts,
            .globally_addressable_scratch,
            .kernarg_preload,
            .lds_barrier_arrive_atomic,
            .ldsbankcount32,
            .lerp_inst,
            .lshl_add_u64_inst,
            .mad_u32_inst,
            .max_hard_clause_length_63,
            .mcast_load_insts,
            .memory_atomic_fadd_f32_denormal_support,
            .min3_max3_pkf16,
            .minimum3_maximum3_pkf16,
            .packed_fp32_ops,
            .packed_tid,
            .permlane16_swap,
            .pk_add_min_max_insts,
            .prng_inst,
            .pseudo_scalar_trans,
            .qsad_insts,
            .restricted_soffset,
            .s_wakeup_barrier_inst,
            .sad_insts,
            .salu_float,
            .scalar_dwordx3_loads,
            .setprio_inc_wg_inst,
            .shader_cycles_hi_lo_registers,
            .sramecc_support,
            .tanh_insts,
            .tensor_cvt_lut_insts,
            .transpose_load_f4f6_insts,
            .vcmpx_permlane_hazard,
            .vgpr_align2,
            .vmem_pref_insts,
            .wait_xcnt,
            .wavefrontsize32,
            .xnack,
            .xnack_support,
        }),
    }